The NRI832 Instruction Set

The NRI832 instruction set is described fairly well in the reference book, but it is slightly incomplete in places. So here is my interpretation of it, with a commentary for things that are unknown or derived from the schematic.

Main Instruction Set

000aaaaa LDA <addr>

Loads the A register with the contents of memory location aaaaa

001aaaaa STA <addr>

Stores the A register into memory location aaaaa. The memory location must be in the TTL Memory from 10000 to 11111 (16..31). If the unit is unexpanded, then this is written to the E register instead.

010aaaaa ADD <addr>

Adds the contents of the memory location aaaaa to the A register. The Overflow flag is set from the carry out of the 8th bit of this addition.

011aaaaa SUB <addr>

Subtract the contents of memory location aaaaa from the A register. This is done in twos complement arithetic - it is equivalent to adding the ones complement of the memory location aaaaa plus one.

The documentation does not say what happens to the overflow flag. As it uses the same hardware as ADD this will be a 'not borrow' result like the 6502 CPU - e.g set if A + ~Mem[aaaaa] + 1 has a carry out.

100aaaaa JMP <addr>

Set the Program Counter to aaaaa

101aaaaa JOM <addr>


Set the Program Counter to aaaaa if the A register is negative (e.g. bit 7 is non zero). There is no flag for this (as for the Z80 say), it simply tests the bit value as is.

110aaaaa JOZ <addr>



Set the Program Counter to aaaaa if the A register is zero. There is no flag for this (as for the Z80 say), it simply tests the accumulator value


111dxccc OPR <instruction>

These are extended instructions rather like on a PDP-8. There are currently eight, defined by the ccc bits. The d bit indicates the direction of the shift (0 = right,1 = left)


Technically the dx bits can have any value (apart from the shift) without affecting the operation. I am standardising the 'x' bit as zero in this project so I can extend the instruction set if I wish to do so. All extensions will be "plausible" (e.g. could be implemented in TTL at the time the machine was designed).


So x should by convention be zero for the 'standard' OPR instructions, and d should be zero for anything other than SHL.

OPR Instructions
 

111xx000 RAB


This rotates the A and B registers. This means, in NRI832 terms, swap them round. The "rotate" probably comes from the serial nature of the original CPU.


1110x001 SHR 


This shifts the A register 1 bit to the right, setting the most significant bit to zero. The least significant bit is lost.


This is a variant of the SHA instruction which does not specify direction (it is specified by bit 4) which I have given the SHR mnemonic to in case I write an Assembler.

111xx010 AND

Logical AND the B register to the A register

111xx011 DCA

Decrement the A register by 1.

This operation uses the serial adder (the ADD and SUB use) but jams the inputs to 1, so it is adding '11111111' binary to the Accumulator. Logically, therefore this should set the Overflow flag accordingly (e.g. it will be set to '1' unless the Accumulator was originally zero, an inverse borrow).

111xx100 CMA

Ones complement the accumulator
 

111xx101 SKC

SKC skips the next instruction to be executed, if the CDX connection is logical '1'.

This is actually unspecified. The documentation says "can be wired to sense practically any logical condition in the computer" and the CDX input (on page 4 of the schematic) actually isn't wired to anything at all on the rest of the schematics. 


It is a reasonable guess that the CDX connection is wired differently for different activities (I do not know what the courseware was) so it could be used to count pulses or something similar. 


Logically the most likely connection is to the overflow line as there is no other way of checking if a carry-out has occurred and there is nothing else to connect it to that makes any kind of sense. The reference document does suggest this. 


However at present it will be a no-operation effectively (e.g. assume CDX is logical zero)
 
111xx110 RAE

Rotates (e.g. exchanges) the A and E registers

111xx111 HLT

Stops the processor from running (if it is free running)

1111x001 SHL

This shifts the A register 1 bit to the left, setting the least significant bit to zero. The most significant bit is lost.


This is a variant of the SHA instruction which does not specify direction (it is specified by bit 4) which I have given the SHL mnemonic to in case I write an Assembler.